[cc] backend regalloc refactor #437
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Pull request overview
This PR refactors the backend register allocation code by extracting it from the architecture-specific codegen modules into dedicated regalloc modules. The register allocation logic for both x86_64 and AArch64 is moved from codegen.rs into new regalloc.rs files, improving code organization and separation of concerns.
Key changes:
- Creates new
regalloc.rsmodules for x86_64 and AArch64 architectures - Moves register definitions, location types, and linear scan register allocator implementations
- Updates imports in
lir.rsandcodegen.rsto use the new regalloc modules - Registers the new modules in architecture-specific
mod.rsfiles
Reviewed changes
Copilot reviewed 8 out of 8 changed files in this pull request and generated 8 comments.
Show a summary per file
| File | Description |
|---|---|
| cc/arch/x86_64/regalloc.rs | New file containing x86_64 register definitions, allocator, and location types moved from codegen.rs |
| cc/arch/x86_64/mod.rs | Adds regalloc module to x86_64 architecture exports |
| cc/arch/x86_64/lir.rs | Updates import to use Reg and XmmReg from regalloc instead of codegen |
| cc/arch/x86_64/codegen.rs | Removes register allocation code (moved to regalloc.rs) and updates imports |
| cc/arch/aarch64/regalloc.rs | New file containing AArch64 register definitions, allocator, and location types moved from codegen.rs |
| cc/arch/aarch64/mod.rs | Adds regalloc module to aarch64 architecture exports |
| cc/arch/aarch64/lir.rs | Updates import to use Reg and VReg from regalloc instead of codegen |
| cc/arch/aarch64/codegen.rs | Removes register allocation code (moved to regalloc.rs) and updates imports |
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1. cc/arch/aarch64/regalloc.rs - Added callee_saved_fp_used() getter (line
915)
2. cc/arch/aarch64/lir.rs - Added new LIR instructions:
- StpFp - Store pair of FP registers (line 587)
- LdpFp - Load pair of FP registers (line 595)
- Emit implementations for both (lines 1310-1334)
3. cc/arch/aarch64/codegen.rs - Full integration:
- Get FP callee-saved registers from allocator (line 280)
- Frame size calculation includes FP callee-saved space (lines 295-297)
- frame_info type extended to (i32, Vec<Reg>, Vec<VReg>) (line 604)
- Prologue saves FP callee-saved registers using stp (lines 435-481)
- Epilogue restores FP callee-saved registers using ldp (lines 702-728)
Key AAPCS64 compliance: Per the ABI, only the lower 64 bits of V8-V15 need
preservation, so we save/restore as d8-d15 (using FpSize::Double).
Changes to cc/arch/x86_64/regalloc.rs: 1. Added block_start_pos tracking (line 656) - needed to detect back edges 2. Added loop back-edge detection (lines 751-772) - identifies branches to earlier blocks 3. Added lifetime extension for loop variables (lines 774-786) - extends last_use for variables that live across loop iterations The logic is identical to AArch64: if a variable is defined before a loop, used inside the loop, and there's a back edge, its live interval is extended to the back edge position. This prevents the register allocator from prematurely freeing registers that are still needed in subsequent loop iterations.
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