[cc] backend regalloc refactor

cc/arch/aarch64/lir.rs

@@ -13,7 +13,7 @@
 // enabling peephole optimizations before final assembly emission.
 //
 
-use super::codegen::{Reg, VReg};
+use super::regalloc::{Reg, VReg};
 use crate::arch::lir::{Directive, EmitAsm, FpSize, Label, OperandSize, Symbol};
 use crate::target::{Os, Target};
 use std::fmt::{self, Write};

cc/arch/aarch64/mod.rs

@@ -12,5 +12,6 @@
 pub mod codegen;
 pub mod lir;
 pub mod macros;
+pub mod regalloc;
 
 pub use macros::get_macros;